1. Technical Field
The present invention relates to a semiconductor device, a semiconductor device design method, a semiconductor device design apparatus, and a program.
2. Related Art
A semiconductor device is equipped with Input/Output (I/O) cells for input and output of signals to an external device. A power potential supply cell and a ground potential supply cell are also provided in the semiconductor device in order to supply electric power to the semiconductor device. These cells are provided along the edge of the semiconductor device in a plan view.
In recent years, as semiconductor vices have become smaller, one side of each semiconductor device has become shorter. Moreover, the number of pins in the semiconductor device is also increasing. Nevertheless, cells cannot be miniaturized below a certain extent. Thus, some studies have been made of a multiple-stage array of the cells.
For example, Japanese Patent Publication No. 3947119 discloses that the arrangement distance between inner peripheral side cells is made larger than the arrangement distance between outer peripheral side cells. Japanese Patent Publication No. 3259763 discloses that power supply interconnects of I/O cells provided in the same column are mutually connected and that a cell located at the inner peripheral side is made smaller than a cell located at the outer peripheral side. Japanese Laid-Open Patent Publication No. 2002-151590 discloses arraying long I/O cells in the longitudinal direction. Japanese Laid-Open Patent Publication No. 2008-141168 discloses that some portions include a multiple-stage array of the cells, whereas the other portions include one stage array of the cells. Japanese Laid-Open Patent Publication No. 2006-147610 discloses that in order to reduce the chip area, one I/O cell is divided into subblocks according to each function and that the arrangement and combination of the subblocks provide a function of one I/O cell.
U.S. Unexamined Patent Application Publication No. 2005/0116356 discloses arraying a ground cell, a power potential supply cell, and an I/O cell in this order from the outer peripheral side and connecting these cells to the inside region using interconnects of a lower layer. U.S. Pat. No. 6,798,075 discloses arraying pads with different voltage levels in different stages and then connecting the plurality of pads to one I/O cell. U.S. Unexamined Patent Application Publication No. 2007/0187808 discloses that a semiconductor chip with a multiple-stage array of cells is disposed on an interconnect substrate and that pads of the cells of the semiconductor chip is connected to interconnects on the interconnect substrate through bonding wires.
As semiconductor devices have become smaller in recent years, one side of each semiconductor device has become short. Additionally, as the number of semiconductor elements integrated in a semiconductor chip increases, the level of functionality realizable by the semiconductor chip has also been improved. In this case, since the number of input and output signals increases, the number of pins in the semiconductor device is also increasing. For this reason, it is necessary to array as many as possible I/O cells at one side of the semiconductor device. Thus, it is necessary to supply a power potential and a ground potential to each stage if cells are arrayed in multiple stages. In general, a power potential supply cell and a ground potential supply cell are provided in each stage. In this case, however, the number of I/O cells decreases as the number of power potential supply cells and the number of ground potential supply cells increase.